Scaling in semiconductor technology has directly resulted in the ability to place an increased number of transistors and other integrated circuit components onto a single chip. This has lead to increased process and manufacturing capabilities. However, the relative variations, and in some cases, the absolute variations, of key parameters have also increased resulting in their greater importance due to their major role in chip functionality, yield and system optimization. Key parameters may include, for example, the resistance value of vias and the threshold voltage of transistors. In order to manage variability in semiconductor integrated circuit technology, characterizations of variability must be implemented in the manufacturing process.
Traditionally, due to the limitations of layout area and testing time, test structures containing only a few elements of the integrated circuit components such as, for example, transistors or a chain of vias, were designed and monitored. More recently, Addressable Parametric Diagnostic (APD) schemes have been utilized together with high speed testing tools. See, for example, U.S. Pat. Nos. 6,503,765 and 6,784,685. APD is a memory-array-like macro in which each cell in the array contains a test structure such as, for example, a via chain. However, questions remain as to whether the data intensive nature and high speed measurement of APD schemes are practical, and whether APD is able to be widely utilized in a manufacturing environment.
In a separate approach, a scheme has been proposed for measuring metal oxide substrate field effect transistor (MOSFET) threshold mismatch, see, for example, K. Terada et al., “A Test Circuit for Measuring MOSFET Threshold Voltage Mismatch,” Microelectronic Test Structures, 2003, International Conference, March 2003, pp. 227-231; and K. Terada et al. “Further Study of V/Sub TH/-Mismatch Evaluation Circuit,” Microelectronic Test Structures, 2004, Proceedings, ICMTS '04, The International Conference, March 2004, pp. 155-159. The test circuits proposed consist of many parallel connected unit cells, in which two nominally identical MOSFETs are serially-connected to each other. The node between the nominally identical MOSFETs is connected to common wiring through a switch. The threshold voltage mismatch for the two MOSFETs is derived from the DC currents flowing through this test circuit, as will be described in greater detail with respect to FIG. 9 below. However, this approach, including experimental demonstrations, was limited to unit cells of two serially-connected nominally identical MOSFETs in their sub-threshold region, and failed to address the broader area of variability measurement.
In summary, the techniques presented above that are currently used in parameter variability measurements fail to address all the requirements for technology development as well as manufacturing process monitoring and control.